(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of forming a high voltage oxide and a select gate poly for a split-gate flash memory cell.
(2) Description of the Related Art
Oxide thickness plays an important role both in terms of electrical strength as well as providing physical isolation between conductive regions in a semiconductor device. More often than not, an oxide layer of a given thickness is formed at once, and the same oxide layer is used for two different components in the same device. A case in point is the portion of the same oxide layer that is used in the forming of the gate oxide of a select transistor in a conventional split-gate memory cellxe2x80x94which will be described in more detail laterxe2x80x94that is also used as the gate oxide of a high voltage peripheral transistor.
Thus, in FIG. 1, where a split-gate flash memory cell is shown, oxide layer (30) is formed over substrate (10), and it extends to a peripheral transistor (70). Oxide layer can be gate oxide and tunnel oxide. However, normally transistor (70) is a high voltage transistor and requires a thicker oxide. If a thicker oxide is formed throughout, then the thicker oxide causes poor current drive for the select transistor (60) shown in FIG. 1, under low voltage operating conditions. It is sometimes the conventional practice to extend the secondary oxide layer (55) shown in FIG. 1 to provide a thicker oxide under transistor (70). However, the resulting oxide thickness is not necessarily the optimized thickness needed for the peripheral transistor, namely, (70). It is disclosed in the present invention a method of forming an optimized high voltage (HV) oxide for a peripheral HV transistor independent of the oxide thicknesses required in other portions, such as for the select transistor, of a split-gate flash memory cell. It is also disclosed that the doping of the HV transistor can be optimized independently of the doping for the select transistor of the flash memory cell.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMS) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. Here, two MOS transistors share a source (25). Each transistor is formed on a semiconductor substrate (10) having a first doped region (20), a second doped region (25), a channel region (23), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). As is known in the art, control gate serves the function of a select transistor. Substrate (10) and channel region (23) have a first conductivity type, and the first (20) and second (25) doped regions have a second conductivity type that is opposite the first conductivity type. In the conventional split-gate flash memory cell shown in FIG. 1, the same gate oxide thickness prevails throughout the substrate, including the HV transistor (70) area.
Different oxide thickness requirements for different areas in the same semiconductor substrate is propelled even more with advances in the ultra large scale integrated (ULSI) circuits. Device geometries of integrated circuits are continually made smaller so that the device density of the entire system can be maximized. This results in, for example, transistors within integrated devices such as MOSFETS having shorter and sorter gate lengths. This in turn necessitates a reduction in gate oxide thickness and operating supply voltage in order to support the minimum gate length without excessively high threshold voltages. The minimum allowable gate oxide thickness for a given device is limited by the time dependent dielectric breakdown of the thin oxide at the desired operating voltage. As a result, the operating voltages applied to the gates of transistors within a particular device must be reduced as the gate oxides within these devices are reduced in thickness, as is known in the art.
Furthermore, it has become necessary to integrate different gate oxide thicknesses onto a single integrated circuit device. This is because, high performance transistors require thinner gate dielectric regions and operate at lower voltages (e.g. 1.8 volts to 2.5 volts), whereas most conventional external peripherals typically require higher operating voltages such as 3.3 volts to 5.0 volts. When interfacing lower voltage high performance MOS transistors to higher voltage devices, input and output (I/O) buffers of the integrated circuit (IC) are typically designed to contain thicker gate dielectric regions that are compatible with the higher external peripheral device voltages. In addition, current micro-controller units (MCUs) and digital signal processors (DSPs) are integrating several different types of technology onto a single integrated circuit. For example, high speed logic, power logic, static random access memory (SRAM), nonvolatile memory (NVM), embedded dynamic random access memory (DRAM), analog circuitry, and other devices and technologies are now being considered for integration onto the same integrated circuit die. Many of these devices require different gate dielectric processing and different gate dielectric thicknesses.
Forming of gate oxide layers having two different thicknesses on the same substrate can be difficult. In U.S. Pat. No. 6,010,929, Chapman teaches a method of forming high voltage (HV) and low voltage (LV) transistors on the same substrate. Hsieh, et al., teach a process for a split-gate flash cell. In another U.S. Pat. No. 5,970,3171, Hsieh, et al., show another method of forming a split-gate flash EEPROM with sharp beak of poly. A split-gate with a source side injection is proposed by Guterman, et al., in U.S. Pat. No. 5,776,810. Lin, et al, in U.S. Pat. No. 5,851,81 and Sung, et al., in U.S. Pat. No. 5,940,706 also show related split-gate flash cell methods.
Thus, conventionally, photolithographic techniques are employed to pattern separately the oxides that are to have different thicknesses. It is often the case, however, that with the required two different oxide thicknesses, there are times when a photoresist mask is placed in proximity to the bare semiconductor substrate. The photoresist is known to cause degradation of the surface of the substrate, which is not desirable especially in the area intended to be used for high performance transistors. It is disclosed in the embodiments of the present invention a method of forming an optimized thickness oxide for a peripheral high voltage transistor without affecting the performance of a split-gate flash memory cell.
It is therefore an object of the present invention to provide a method of forming a high voltage oxide and a select gate poly for a split-gate flash memory cell.
It is another object of the present invention to provide a method of forming two different oxides for two different areas on the same substrate.
It is still another object of the present invention to provide a method of forming an optimized oxide thickness for a high voltage transistor independently of the thickness required for a select transistor of a memory cell.
It is yet another object of the present invention to provide method of optimizing the doping characteristics of a select transistor of a cell independently of that of a peripheral transistor.
These objects are accomplished by providing a substrate having a cell area and a peripheral area; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said first gate oxide layer; forming a nitride layer over said first polysilicon layer; forming a first photoresist layer over said nitride layer; patterning said first photoresist layer to define floating gate in said cell area; etching said nitride layer through said patterning in said first photoresist layer and forming opening in said nitride layer reaching said first polysilicon layer; removing said first photoresist layer; performing thermal oxidation of said first polysilicon layer exposed in said opening reaching said first polysilicon layer to form poly-oxide; removing said nitride layer; etching said first polysilicon layer using said poly-oxide as a hard mask to form a floating gate in said cell area and removing said first polysilicon layer from said peripheral area; forming a second photoresist layer over said substrate and patterning to define source region in said cell area; performing ion implantation through opening in said second patterned photoresist mask to form source region in said cell area within said substrate; removing said second photoresist layer; forming a tunneling oxide layer over said floating gate in said cell area; forming a second cell polysilicon layer over said tunneling oxide layer over said cell area; growing an HV oxide layer over said substrate including over said cell polysilicon layer over said cell area and over said gate oxide layer over said peripheral area; forming a peripheral polysilicon layer over said HV oxide layer over said peripheral area; forming a third photoresist layer over said substrate to have patterns corresponding to a control gate over said cell area and a peripheral gate over said peripheral area; etching said peripheral polysilicon layer through said patterns in said third photoresist layer to form said peripheral gate over said HV oxide layer over said peripheral area; and etching said second cell polysilicon layer through said patterns in said third photoresist layer to form said control gate over said tunneling oxide layer over said cell area.